Z16C3220FSG
Features
- Two full-capacity 20 MHz DMA channels, each with 32-bit addressing and 16-bit data transfers
- DMA modes include single buffer, pipelined, array - chained and linked-array chained
- Ring buffer feature supports circular queue of buffers in memory
- Programmable throttling of DMA bus occupancy in Burst Mode with bus occupancy time limitation
- 0 to 20 Mbit/sec, full-duplex channel, with two Baud Rate Generators and a digital Phase-Locked Loop for clock recovery
- 32-byte data FIFOs for receiver and transmitter
- Up to 12.5 MByte/sec (16-bit) data bus bandwidth
- Multiprotocol operation under program control with independent mode selection for receiver and transmitter
- External Character Sync Mode for receive
- Receive and Transmit time slot assigners for ISDN, T1 and E1 (CEPT) applications
- 8-bit general-purpose port with transition detection
- 68-pin PLCC package
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