Z0853606PSG

Features

  • Two independent 8-bit, double-buffered bidirectional I/O ports plus a 4-bit special-purpose I/O port. I/O ports feature programmable polarity, programmable direction (Bit mode),
  • Four handshake modes, including 3-Wire (like the IEEE-488).
  • REQUEST/WAIT signal for high-speed data transfer.
  • Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller.
  • Three independent 16-bit counter/timers with up to four external access lines per counter/timer (count input, output gate, and trigger), and three output duty cycles (pulsed, one-shot, and square-wave), programmable as retriggerable or nonretriggerable.
  • Easy to use since all registers are read/write.
Z08536 CIO Block Diagram

Related Links
• Documentation • Samples
Parts
Part NumberPackageStatus
Z0853606VSGPLCCEOL
Z0853606VEGPLCCEOL
Part NumberPackageStatus
Z0853606PSG EOL

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