Features
- Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core
- 10/100 BaseT Ethernet Media Access Controller (EMAC)
- 256KB Flash memory
- 16KB SRAM (8KB user and 8KB Ethernet)
- Low-power features including SLEEP mode, HALT mode and selective peripheral power-down control
- Two Universal Asynchronous Receivers/Transmitters (UARTs) with independent Baud Rate Generators (BRGs)
- Serial Peripheral Interface (SPI) with independent clock rate generator
- I2C with independent clock rate generator
- IrDA-compliant infrared encoder/decoder
- Fixed-priority vectored interrupts (both internal and external) and interrupt controller
- Four 16-bit Counter/Timers with prescalers and direct input/output drive
- Watch-Dog Timer with internal oscillator clocking option
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Zdots SBC ASSP Architecture
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