Zilog’s Enhanced Serial Communication Controllers (ESCCs) are dual- and single-channel multiprotocol serial communications peripherals that are pin and software compatible members of Zilog’s SCC family.
These ESCC controllers provide support for multiple asynchronous formats, synchronous/isochronous formats, byte-oriented synchronous protocols such as MONOSYNC and BISYNC, and bit-oriented synchronous protocols such as HDLC/SDLC and external sync..
For HDLC/SDLC communications applications, Zilog’s ESCC controllers provide support up to the frame level to reduce the burden on the host CPU. This support includes automatic opening and closing flag transmission, automatic CRC generation, error checking and an SDLC Frame Status FIFO to support DMA-based applications.
An integrated Digital Phase Locked Loop can be programmed to recover the clock from NRZI-, FM0-, FM1- and Manchester-encoded data.
To reduce processor interrupt overhead, the ESCC provides an 8-byte receive FIFO and 4-byte transmit FIFO and can be used in polled interrupts of DMA-driven applications.
For products requiring asynchronous communications, the ESCC supports data formats of 5 to 8 bits per character and can use 1X, 16X, 32X or 64X clock modes. All error checking and break generation/ detection is handled automatically.
The Z85230, Z80230 are 5V dual-channel devices. The Z8523L is a dual-channel 3V device, and the Z85233 (EMSCC) is a single-channel device that provides a smaller 44-pin PQFP footprint.