Multi-Protocol Enhanced Serial Communications

 

         
         
 


Multi-Protocol Serial Communications Solutions

Zilog’s Enhanced Serial Communications Controllers: Z85230/Z80230/Z8523L/Z85233

 

Application Notes

Using SCC & ESCC Controllers
•  Boost your System Performance Using the Zilog ESCC Controller (AN0300)
•  The Zilog Datacom Family with the 80186 CPU (AN0097)


ESCC Features and Benefits
   
•  Multiple Protocol Support: Asynchronous, Mono-Sync, Bi-Sync, External Sync, Isosynchronous, and HDLC/SDLC
•  Multiple Encoding Modes: NRZ, NRZI, FM0, FM1, and Manchester
•  4-Byte Transmit FIFO
•  8-Byte Receive FIFO
•  One or two independent full-duplex channels with seperate baud rate generator (BRG) and a digital phase locked loop (DPLL) for each channel
•  Flexible clocking scheme provides programmable DTE/DCE Operation
•  Up to 5 Mbps Data Rate
5V and 3V versions availalble
CRC-16 or CRC-CCITT error checking and generation
Pin-compatible with the industry standard SCC
Asynchronous capabilities:
  -  5, 6, 7,  or 8 bits/character
  -  1, 1.5, or 2 Stop bits
  -  Odd or Even parity
  -  Parity, Overrun, and Framing Error detection
Character-oriented synchronous capabilities:
  -  Internal or external synchronization
  -  1 or 2 SYNC characters (6 or 8 bits/character)
  -  Cyclic redundancy check (CRC-16, CRC-CCITT) generation/detection
•  SDLC/HDLC Capabilities:
  -  Automatic zero insertion and detection
  -  Automatic flag insertion between messages
  -  Address field recognition for loop mode
  -  CRC generation/detection

 

ESCC Block Diagram

 

 

 

   
 


Zilog’s Enhanced Serial Communication Controllers (ESCCs) are dual- and single-channel multiprotocol serial communications peripherals that are pin and software compatible members of Zilog’s SCC family.

These ESCC controllers provide support for multiple asynchronous formats, synchronous/isochronous formats, byte-oriented synchronous protocols such as MONOSYNC and BISYNC, and bit-oriented synchronous protocols such as HDLC/SDLC and external sync..

For HDLC/SDLC communications applications, Zilog’s ESCC controllers provide support up to the frame level to reduce the burden on the host CPU. This support includes automatic opening and closing flag transmission, automatic CRC generation, error checking and an SDLC Frame Status FIFO to support DMA-based applications.

An integrated Digital Phase Locked Loop can be programmed to recover the clock from NRZI-, FM0-, FM1- and Manchester-encoded data.

To reduce processor interrupt overhead, the ESCC provides an 8-byte receive FIFO and 4-byte transmit FIFO and can be used in polled interrupts of DMA-driven applications.

For products requiring asynchronous communications, the ESCC supports data formats of 5 to 8 bits per character and can use 1X, 16X, 32X or 64X clock modes. All error checking and break generation/ detection is handled automatically.

The Z85230, Z80230 are 5V dual-channel devices. The Z8523L is a dual-channel 3V device, and the Z85233 (EMSCC) is a single-channel device that provides a smaller 44-pin PQFP footprint.

 

 
 

Resources & Documentation

 

Order Samples

Product Brief: PB0004

 

Z85233 Product Specification (DC4058)

Z80230/Z85230/Z8523L Product Specification (PS0053)

 

Product Information  

Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual (UM0109)

         Technical Support

 

Zilog Forum

 

 

 

 

 




 

 


 

 

 

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